amd64_cache.pl
Opt-in block-local caching of private integer frame homes in r10/r11. This is not instruction selection or general register allocation. All eight bytes of a home stay together, even when a read uses only its low word. Every alias must be w/l. Pointers, roots, phi shadows, local storage and ABI bookkeeping retain their original homes.
Each region starts and ends with synchronized memory. Calls, control flow, frame changes and non-rewritable memory accesses separate regions. Loads whose complete destination value is already present are removed first; a low-word load still has to zero its destination's high half. A linear scan assigns a home's entire first-to-last reference interval; every intervening store replaces its cached version. There is no eviction: intervals under pressure keep their stack representation. The fixed register order and interval order make output deterministic.
Unknown original forms or explicit uses of the cache bank keep the whole implementation unchanged. A translation-check failure is an error, never a reason to silently hide an allocator bug.
Report is stack, excluded(setjmp|unsupported), or cached(Homes,Regions). Regions counts regions changed by load removal or an assigned interval.
At most one association per ordinary register: part of a current home, and whether the register's upper half is zero. A store invalidates all associations with that physical home, even if its temporary has changed. This bounded forward analysis is separate from the checker's symbols.