Independent translation validation for the block-local scalar cache. There are no allocation intervals, slot assignments or eviction plans here. The two streams execute together on symbolic register and home contents; only the three eligible moves may differ, and a load may be absent when its complete result is already in its destination. All other lines match exactly, including flags, failure arguments and control flow.

Ordinary registers have one shared symbolic map: a changed load must prove equality before writing it. Homes have separate reference and actual contents, and each cache register holds a full 64-bit value. Values have independent low/high halves, so a 32-bit read zero-extends its destination without truncating the cached home. Unchanged opaque instructions give their written families fresh, shared symbols.

Before every boundary all homes must agree. Afterward we forget the cache and start with arbitrary common homes/registers. This proves each straight-line region for every possible entry state, including entries from other branches; it does not follow textual fallthrough through a label. Unmentioned/noneligible homes cannot differ because every instruction touching them is unchanged and a boundary. The home map is sparse: untouched homes have a common epoch-tagged default. Boundaries scan only homes written in that region, not the frame.